1. Field of the Invention
The present invention relates to a structure of a shorting bar used to test an electrical state of a liquid crystal display device (or LCD) during manufacture of an including thin film transistors (or TFTs) and a method for forming the same. More specifically, the present invention relates to a liquid crystal display apparatus including a first shorting bar connected to odd-numbered gate lines and a second shorting bar connected to even-numbered gate lines of TFTs, and a method for forming the same.
2. Description of the Background Art
Among display devices for showing visual images on a screen, thin film flat panel display devices are highly favored because of their light weight and easy adaptability. Recent research activities have focused on the development of liquid crystal display devices because of their high resolution and fast response time suitable for display of motion picture images.
A liquid crystal display device works by using polarization and optical anisotropy of a liquid crystal. By controlling the orientation of rod-shaped liquid crystal molecules via a polarization technique, transmission and interception of a light through the liquid crystal molecules are achieved due to the anisotropy of the liquid crystal. Active matrix liquid crystal displays (or AMLCDs) having TFTs arranged in a matrix pattern and pixel electrodes connected to the TFTs provide high quality images and are now widely used. The structure of a conventional AMLCD will now be described.
Generally, a liquid crystal display device is made of two panels which include several elements and are arranged to face each other with a liquid crystal material located therebetween. The first of the two panels is a color filter panel which includes a sequential arrangement of red, blue and green color filters arranged on a transparent substrate at pixel positions in a matrix pattern. Between these color filters, black matrixes are formed in a lattice pattern. On the color filters, a common electrode is formed.
The second of the panels is an active panel and includes pixel electrodes positioned in a matrix pattern of rows and columns on a transparent substrate. Along a column direction of the pixel electrodes, scan bus lines are arranged, and along a row direction of the pixel electrodes, data bus lines are arranged. At a corner of a pixel electrode, a TFT for driving the pixel electrode is provided. A gate electrode of the TFT is connected with a scan bus line which is commonly referred to as a gate line. A source electrode of the TFT is connected with a data bus line which is commonly referred to as a source line. Additionally, a gate pad is formed at the end portion of each gate line, and a source pad is formed at the end portion of each source line.
The color filter panel and the active panel are arranged to face each other and are bonded together with a certain distance located therebetween (i.e., a cell gap) Liquid crystal material fills the cell gap to complete a liquid crystal panel of an LCD.
The method of manufacturing a liquid crystal display device is very complicated including many processes. As mentioned above, the LCD is manufactured by making a color filter panel and an active panel, joining the color filter panel and the active panel together and injecting the liquid crystal material between the color filter panel and the active panel. The method of manufacturing an active panel having TFTs and pixel electrodes is even more complicated especially if the active panel has a shorting bar for providing protection from static electricity and for testing the manufactured active panel. Therefore, it is important to simplify the method for manufacturing an active panel to reduce the possibility of defects during the manufacture process.
A conventional method for manufacturing an active panel having a shorting bar is described with reference to FIG. 1 showing a plan view of a conventional active panel and FIGS. 2a-2f showing cross sectional views taken along line II--II of FIG. 1.
Aluminum or an aluminum alloy is deposited on a transparent substrate 1, such as a non-alkalic glass to make an aluminum layer. A low resistance gate line 13a and a low resistance gate pad 15a are formed by patterning the aluminum layer. The low resistance gate line 13a extends along the row direction of the pixels which are arranged in a matrix array. The low resistance gate pad 15a is disposed at the end of the low resistance gate line 13a, as shown in FIG. 2a.
A metal formed of one of chromium, molybdenum, tantalum or antimony is deposited on the substrate having the low resistance gate line 13a and the low resistance gate pad 15a. A gate line 13, a gate pad 15, a gate electrode 11 and an odd-numbered gate shorting bar (or odd shorting bar) 61 are formed by patterning the metal layer. The gate line 13 covers the low resistance gate line 13a. The gate pad 15 covers the low resistance gate pad 15a. The gate electrode 11 extends from the gate line 13 as seen in FIG. 1 and is formed at one corner of the pixel. The odd gate shorting bar 61 is disposed along the array direction of the gate line 13. In general, the shorting bar 61 is disposed at the edge of the substrate 1 of the active panel, as shown in FIG. 2b.
A first inorganic material such as silicon nitride or silicon oxide is deposited on the substrate having the gate elements including the gate line 13, the gate pad 15 and the gate electrode 11 so as to make a gate insulating layer 17. An intrinsic semiconductor material such as pure amorphous silicon and an extrinsic semiconductor material such as impurity doped amorphous silicon are sequentially deposited thereon. A semiconductor layer 33 and a doped semiconductor layer 35 are formed by patterning the intrinsic and extrinsic semiconductor layers on the gate electrode 11, as shown in FIG. 2c.
A metal such as chromium is deposited on the substrate having the doped semiconductor layer 35. A source line 23, a source electrode 21 and a drain electrode 31 are formed by patterning the metal layer. The source line 23 is substantially perpendicularly intersecting with the gate line 13 and arranged along the column direction. The source electrode 21 extends from the source line 23 as seen in FIG. 1 and overlaps one side of the gate electrode 11 wherein the semiconductor layer 33 and the doped semiconductor 35 are sandwiched therebetween. The drain electrode 31 faces the source electrode 21 and overlaps the other side of the gate electrode 11. The doped semiconductor layer 35 is separated into two parts using the source electrode 21 and the drain electrode 31 as a mask. The doped semiconductor layer 35 is in ohmic contact with the source electrode 21 and the drain electrode 31, as shown in FIG. 2d.
A passivation layer 137 is formed by depositing an inorganic insulating material such as a silicon nitride or a silicon oxide on the substrate having the source electrode 21, the drain electrode 31 and so on. A drain contact hole 71 exposing a portion of the drain electrode 31 is formed by patterning the passivation layer 137. A gate contact hole 51 exposing a portion surface of the gate pad 15 is formed by patterning the passivation layer 137 and the gate insulating layer 17 covering the gate pad 15, as shown in FIG. 2e.
A transparent conductive material such as an ITO (Indium Tin Oxide) is deposited on the passivation layer 137 and patterned to form a pixel electrode 41, a gate pad terminal 57 and an even-numbered gate shorting bar (or even shorting bar) 63. The pixel electrode 41 is connected to the drain electrode 31 through the drain contact hole 71 and is disposed at the pixel area. The gate pad terminal 57 is connected to the gate pad 15 through the gate contact hole 51. The even shorting bar 63 is disposed in parallel with the odd shorting bar 61 and connected to the even-numbered gate pads 15 which are connected to the even-numbered gate lines 13, as shown in FIG. 2f.
The structure of the shorting bar made according to the conventional method of manufacturing an active panel is formed as follows. The odd-numbered gate pads are connected to each other through the odd gate shorting bar which is simultaneously formed with the gate line and the gate pad. A gate insulating layer and a passivation layer are disposed thereon. The even gate shorting bar connected to the even gate pad 15 and the even gate line 13 is then disposed on the passivation layer 137. Then, an even/odd line test is done to determine which line is cut and/or shorted with any other line so as to detect defects.
As described above, the conventional method for manufacturing the active panel comprises six masking steps or processes. Using this method, the odd gate line group and the even gate line group are in different electrical potential states from a time or step when forming the odd shorting bar to a time or step when forming the even shorting bar. So, when static electricity is created at the separated gate line groups, the gate insulating layer can be damaged and/or certain gate lines can be cut by the difference in the static electricity.